Note that a “wafer” means a structure that may include one or several layers. In the case of a multi-layer wafer, the different layers may have been associated with each other by any type of technique known in itself (layer transfer, gluing, epitaxy, etc.). Thus, a multi-layer wafer is such a structure that contains several layers. And the wafers concerned by this invention are wafers comprising a thin surface layer (made of a material such as silicon) for applications in micro-electronics. Remember that the useful layer is generally a surface layer of the wafer, on which components will be created. Such a surface layer is generally considered as the working surface of the wafer. This layer and its working surface must be of very good quality and free from defects for optimum results.
For applications in microelectronics, it is frequently necessary to perform heat treatment of the wafer—for example heat treatment designed to improve the surface condition of the surface layer of the wafer or thinning by sacrificial oxidation. Surface treatments are also known involving a high temperature heat treatment. The term “high temperature heat treatment” in this text denotes a heat treatment in which at least some phases are carried out at temperatures of several hundred degrees, for example exceeding 750° C. for silicon films in a silicon on Quartz (SOQ—Silicon On Quartz) structure. For different materials, high temperatures can exceed 500° C., 1000° C. or even 1100° C. Note that this high temperature heat treatment definition is not absolute: it is simply given in the context of this text, and it can cover other temperature ranges outside the context of the invention and the previously mentioned typical temperatures.
This type of heat treatment can be carried out according to an RTA (Rapid Thermal Annealing) mode, for a limited time (of the order of a few seconds to a few minutes only). But RTA mode is not limitative and the invention is applicable to any other type of high temperature heat treatment. For example, this type of heat treatment may be applied to wafers concerned by the invention. Other types of heat treatment may be intended to modify the structure of the wafer, and/or to improve the surface condition of the wafer. For example surface treatments involving smoothing annealing are also known. In particular, this type of annealing lowers the surface roughness of a surface layer of a semiconducting material (for example such as silicon) to values compatible with specifications in force in the semiconducting industry.
Thus, one process well adapted to this effect in the case of a surface layer of silicon, consists of performing a smoothing annealing on the wafer comprising the layer, under a reducing atmosphere and, particularly under a hydrogen atmosphere) at a high temperature (that may be more than 950° C. and, for example, 1100° C.). “Smoothing annealing” is thus defined as being annealing carried out under a reducing atmosphere at high temperature—and more precisely at a temperature of the order of 950° C. or more. Smoothing annealing is thus a particular form of high temperature heat treatment. This type of annealing can be carried out for a relatively long time (for example, on the order of two hours). It can also be done in RTA mode at a very high temperature (of the order of 1100° C. or more), for a duration of only a few seconds to a few minutes. This type of annealing smoothes the surface of the wafer. It can also cure some structural defects.
According to known processes, this type of high temperature heat treatment is done on the wafer once it has been created (in other words once operations have been carried out in advance—for example transfer of layers and gluing and/or epitaxy—necessary for creation of the multi-layer wafer). However, these known high temperature heat treatments cannot be used on all types of wafers, since there are some limitations associated with them.
The application of this type of high temperature heat treatment to the treatment of single-layer wafers, or multi-layer wafers in which the different layers have differential thermal characteristics, can be problematic. Note that “differential thermal characteristics” means that the different layers of the wafer behave or respond differently during exposure to a given thermal budget or other high temperature heat treatment. This type of differential generally corresponds to a difference in the coefficients of thermal expansion of materials forming the different layers of the wafer, combined with dimensional characteristics of these layers. And more precisely, in the context of this text, “differential thermal characteristics” of a multi-layer structure are characterized as follows for the purposes of this text:                at least some layers of the structure are associated with different coefficients of thermal expansion, and        there is at least one layer with a significant thickness close to the surface layer (in this case the term “significant thickness” is defined as being a thickness of at least an order of magnitude greater than (namely 10 times greater than) the thickness of the surface layer) that is associated with a coefficient of thermal expansion significantly different from the coefficient of thermal expansion associated with the surface layer.        
“Thermal Budget” is used in the present invention to mean the amount of thermal energy to be applied to a substrate that includes a weakened zone for thermally detaching or cleaving of the substrate at the weakened zone. This is equal to 100% of the necessary energy at which detachment occurs thermally. The temperature-time-dependency of the thermal detachment budget follows Arrhenius Law in which the reciprocal of the annealing time is proportional to the exponent of the reciprocal of the annealing temperature. The budget of thermal detachment of heterogeneous bonded structures is dependent on a number of material, environmental and technological parameters such as the type of material, implantation conditions and bonding conditions.
An SOQ type wafer, comprising a thin surface layer of silicon directly associated with a Quartz support layer with a significant thickness, is thus a typical example of such a structure for which the layers have differential thermal characteristics. In the case of this type of wafer that relaxes after exposure to a large thermal budget (such as thermal budgets that occur with the treatments mentioned above), the thin surface layer of silicon recovers a significant part of the mechanical stresses generated by exposure of the wafer to the thermal budget. In this case, the thin surface layer of silicon, for which the coefficient of thermal expansion is of the order of 2.5×10−6 K−1, which is five times greater than the corresponding value for the subjacent Quartz layer which is of the order of 0.5×10−6 K−1, naturally tends to expand to relax stresses caused by heating.
Note that the coefficient of thermal expansion is defined as being a dimensional variation compared with a reference dimension, per degree of temperature difference. This coefficient is therefore expressed in K−1. But at the same time, the subjacent layer of Quartz to which the surface layer of silicon is fixed does not tend to expand in the same way, and this applies stresses to the surface silicon layer.
In the frequent case in which the surface of the thin layer of silicon includes defects (corresponding to “initial” defects that will be defined in more detail in the remainder of the text), such defects vary under the effect of the said stresses to produce secondary defects of the types defined below, e.g., dislocation type defects.
A wafer for which only a very thin buried layer has a coefficient of thermal expansion significantly different from the coefficient of thermal expansion of the material in the surface layer would not correspond to the definition of a wafer given above for which the layers have “differential thermal characteristics”. A conventional SOI (Silicon On Insulator) type wafer is thus an example of a wafer comprising a surface layer of silicon, under which there is firstly a very thin layer of SiO2, then a thick support layer that is typically made of silicon. In this case, the buried layer SiO2 is associated with a coefficient of thermal expansion that is significantly different from the coefficient of thermal expansion associated with the silicon surface layer, but no secondary defect generation is observed like that mentioned above.
In the case of SOI, the SiO2 layer is buried between two silicon layers that have thicknesses comparable to the SOI layer or are thicker. The very thin layer of SiO2 under these conditions cannot “impose” its mechanical behavior when exposed to high thermal stresses. Finally, note that it would certainly be possible to observe secondary defects of the dislocation type in the layer of SiO2 itself, but since the material in this layer is amorphous, it does not generate any dislocation type crystalline defects.
Returning to the presentation of the problem that the invention is intended to solve, when a wafer for which the layers have a differential thermal characteristic receives a large thermal budget, at least one of the layers of the wafer may be affected by high mechanical stresses due to the difference in expansion of the different layers under the effect of the received heat load. Remember that the different layers in a wafer remain fixed to each other.
The appearance of “secondary” defects in SOQ wafers has been observed following high temperature heat treatment like that mentioned above (for example, possibly a smoothing annealing, a heat treatment under neutral gas, oxidation, etc.). The term “quartz” as used in this specification means molten silica. In the example of an SOQ structure, the observed defects are located in the silicon film and in particular are crystalline defects corresponding to “secondary defects”, since they are generated during the high temperature heat treatment and are related to the initial defects already present in the wafer. Note that in particular, secondary defects may be dislocation type defects, or other crystalline defects associated with initial defects.
“Initial defects” means defects that are already present in materials from which the wafer is composed, or defects generated during one of the steps in initial manufacture of the wafer, before application of the heat treatment associated with appearance of secondary defects (in particular, these initial defects may be sharp edges caused by the strong roughness after detachment of the wafer from a donor substrate).
In general, the appearance of secondary defects in multi-layer wafers has been observed with differential thermal characteristics when the wafers are exposed to a high temperature heat treatment step (for example, the heat treatment may be a smoothing annealing or an RTA treatment, or an oxidation annealing, or in general a high temperature heat treatment). This undesirable effect is shown in FIGS. 1 and 2, which represent observations obtained by TEM (Transmission Electronic Microscopy) on a section through two SOQ wafers (one control indicating the scale of the figure in its bottom left corner). These two figures show a section through the upper part of an SOQ wafer on which a high temperature heat treatment has been conducted. This top part corresponds to the surface layer of Si, and to (at least part of) the SiO2 layer inserted between the surface layer of Si and the Quartz support of the wafer (support not shown).
Thus, FIG. 1 illustrates a dislocation passing through the entire thickness of the surface layer of crystalline silicon (separated from a quartz layer that is not shown on the figures and is located below an SiO2 layer). This type of dislocation is obviously a very serious defect for the silicon surface layer.
FIG. 2 illustrates a loop dislocation 20 that also creates a serious disadvantage. Note that this type of defect generated by smoothing annealing and sometimes extending through the entire thickness of the surface layer (400 nm in the example in FIG. 1) cannot be completely eliminated by thinning the layer, for example by polishing after the said annealing. This type of defect appears particularly when the surface of the multi-layer wafer has initial defects before being exposed to annealing.
In this case, the initial defects are involved in secondary defect generation mechanisms (of the dislocation type in FIGS. 1 and 2) under the effect of mechanical stresses resulting from exposure to a heat budget of the multi-layer wafer with differential thermal characteristics, starting from initial defects already present in the wafer before the high temperature heat treatment. For example, the initial defects might be disturbances on the wafer surface. These initial defects may have been created during previous treatment steps applied to the wafer.
FIG. 3 thus illustrates the layer of silicon in the SOQ wafer in FIGS. 1 and 2 before a high temperature heat treatment was applied to it, with this FIG. 3 showing a disturbed silicon surface. The disturbances on this surface layer may for example correspond to initial defects that will be involved during a high temperature heat treatment in the generation of secondary defects.
Thus, there is a need to minimize or even eliminate such secondary defects. In addition, there is a need to avoid generating defect lines during high temperature heat treatments of various wafers. The present invention now satisfies these needs.